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ST
Sitronix
Features
!" 5 x 8 and 5 x 11 dot matrix possible !" Low power operation support: -- 2.7 to 5.5V !" Wide range of LCD driver power -- 3.0 to 11V !" Correspond to high speed MPU bus interface -- 2 MHz (when VCC = 5V) !" 4-bit or 8-bit MPU interface enabled !" 80 x 8-bit display RAM (80 characters max.) !" 9,920-bit character generator ROM for a total of 240 character fonts -- 208 character fonts (5 x 8 dot) -- 32 character fonts (5 x 11 dot) !" 64 x 8-bit character generator RAM -- 8 character fonts (5 x 8 dot) -- 4 character fonts (5 x 11 dot)
ST7066
Dot Matrix LCD Controller/Driver
!" 16-common x 40-segment liquid crystal display driver !" Programmable duty cycles -- 1/8 for one line of 5 x 8 dots with cursor -- 1/11 for one line of 5 x 11 dots & cursor -- 1/16 for two lines of 5 x 8 dots & cursor !" Wide range of instruction functions: Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift !" Pin function compatibility with HD44780, KS0066 and SED1278 !" Automatic reset circuit that initializes the controller/driver after power on !" Internal oscillator with external resistors !" Low power consumption !" QFP80 and Bare Chip available
Description
The ST7066 dot-matrix liquid crystal display controller and driver LSI displays alphanumeric, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. The ST7066 has pin function compatibility with the HD44780, KS0066U and SED1278 that allows the user to easily replace it with an ST7066. The ST7066 character generator ROM is extended to generate 208 5 x 8 dot character fonts and 32 5 x 11 dot character fonts for a total of 240 different character fonts. The low power supply (2.7V to 5.5V) of the ST7066 is suitable for any portable battery-driven product requiring low power dissipation. The ST7066 LCD driver consists of 16 common signal drivers and 40 segment signal drivers which can extend display size by cascading segment driver ST7065 or ST7063. The maximum display size can be either 80 characters in 1-line display or 40 characters in 2-line display. A single ST7066 can display up to one 8-character line or two 8-character lines.
Product Name
ST7066-0A ST7066-0B
Support Character
English / Japan English / European
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ST7066
Block Diagram
OSC1 Reset Circuit CPG
OSC2
CL1 CL2 M Timing Generator D
Instruction Register (IR) RS RW E Instruction Decoder 40-bit shift registe r 40-bit latch circuit Segment Signal Driver MPU Interface Display data RAM (DDRAM) 80x8 bits 16-bit shift registe r Common Signal Driver
COM1 to COM16
SEG1 to SEG40
Address Counter DB4 to DB7 Input/ Output Buffer
DB0 to DB3
Data Register (DR) Busy Flag
LCD Drive Voltage Selector
Character generator RAM (CGRAM) 64 bits
Character generator ROM (CGROM) 9,920 bits
Cursor and Blink controller
GND
Parallel/Serial converter and Attribute Circuit
Vcc
V1
V2
V3
V4
V5
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Pad Arrangement
1
80
64
ST7066
"ST7066" Marking : easy to find the PAD
(0,0)
Chip Size : 2300x3000 Coordinate : Pad Center Origin : Chip Center Pad Size : 90x90 Unit : um
24
41
Subtrate:VDD
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Pad Location Coordinates
Pad No. Function X Y Pad No. Function X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 Vcc M D RS RW E DB0 DB1
-1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -910 -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 910
1400 1270 1140 1020 900 780 660 540 420 300 180 60 -60 -180 -300 -420 -540 -660 -780 -900 -1020 -1140 -1270 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23
1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 910 780 660 540 420 300 180 60 -60 -180 -300 -420 -540 -660 -780 -910
-1400 -1270 -1140 -1020 -900 -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 900 1020 1140 1270 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400
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Pin Functions
NAME RS NUMBER I/O 1 I INTERFACED WITH MPU FUNCTION Select registers. 0: Instruction register (for write) Busy flag: address counter (for read) 1: Data register (for write and read) Select read or write. 0: Write 1: Read Starts data read/write. Four high order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7066. DB7 can be used as a busy flag. Four low order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7066. These pins are not used during 4-bit operation. Clock to latch serial data D sent to the extension driver Clock to shift serial data D Switch signal for converting the liquid crystal drive waveform to AC Character pattern data corresponding to each segment signal Common signals that are not used are changed to non-selection waveform. COM9 to COM16 are non-selection waveforms at 1/8 duty factor and COM12 to COM16 are non-selection waveforms at 1/11 duty factor. Segment signals Power supply for LCD drive VCC - V5 = 11 V (Max) VCC : 2.7V to 5.5V, GND: 0V When crystal oscillation is performed, a resistor must be connected externally. When the pin input is an external clock, it must be input to OSC1.
R/W E DB4 to DB7
1 1 4
I I I/O
MPU MPU MPU
DB0 to DB3
4
I/O
MPU
CL1 CL2 M D
1 1 1 1
O O O O
Extension driver Extension driver Extension driver Extension driver
COM1 to COM16
16
O
LCD
SEG1 to SEG40 V1 to V5 VCC , GND OSC1, OSC2
40 5 2 2
O -
LCD Power supply Power supply Oscillation resistor clock
Note: 1. Vcc>=V1>=V2>=V3>=V4>=V5 must be maintained 2. Two clock options:
R=91K (Vcc=5V) R=75K
OSC1
1
OSC2
1
OSC1
1
OSC2
1
R
Clock input
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FUNCTION DESCRIPTION
System Interface This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input pin in 4-bit/8-bit bus mode. Table 1. Various kinds of operations according to RS and R/W bits. RS RW Operation L L Instruction Write operation (MPU writes Instruction code into IR) L H Read Busy Flag(DB7) and address counter (DB0 ~ DB6) H L Data Write operation (MPU writes data into DR) H H Data Read operation (MPU reads data from DR)
Busy Flag (BF) When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High.
Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.
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Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal. !" 1-line display (N = 0) (Figure 2) When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the ST7066, 8 characters are displayed. See Figure 3. When the display shift operation is performed, the DDRAM address shifts. See Figure 3.
High Order bits
Low Order bits
Example: DDRAM Address 4F 1 0 0 1 1 1 1
AC AC6 AC5 AC4 AC3 AC2 AC1 AC0
Figure 1 DDRAM Address
Display Position 1 (Digit) 00 DDRAM Address
2
3
4
5
6
78
79
80
01
02
03
04
05
....................
4D
4E
4F
1Figure 2 1-Line Display
Display Position DDRAM Address
1
2
3
4
5
6
7
8
00
01
02
03
04
05
06
07
For Shift Left
01
02
03
04
05
06
07
08
For Shift Right
4F
00
01
02
03
04
05
06
18Figure 3 1-Line by 8-Character Display Example
!" 2-line display (N = 1) (Figure 4) Case 1: When the number of display characters is less than 40 x 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the ST7066 is used, 8 characters x 2 lines are displayed. See Figure 5.
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When display shift operation is performed, the DDRAM address shifts. See Figure 5.
Display Position
1
2
3
4
5
6
38
39
40
00 DDRAM Address 40 (hexadecimal)
01 41
02 42
03 43
04 44
05 45
.................... ....................
25 65
26 66
27 67
2Figure 4 2-Line Display
Display Position DDRAM Address
1
2
3
4
5
6
7
8
00 40
01 41
02 42
03 43
04 44
05 45
06 46
07 47
For Shift Left
01 41
02 42
03 43
04 44
05 45
06 46
07 47
08 48
For Shift Right
27 67
00 40
01 41
02 42
03 43
04 44
05 45
06 46
28Figure 5 2-Line by 8-Character Display Example Case 2: For a 16-character x 2-line display, the ST7066 can be extended using one 40-output extension driver. See Figure 6. When display shift operation is performed, the DDRAM address shifts. See Figure 6.
Display
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Position DDRAM Address
00 40
01 41
02 42
03 43
04 44
05 45
06 46
07 47
08 48
09 49
0A 4A
0B 0C 0D 0E 4B 4C 4D 4E
0F 4F
For Shift Left
01 41
02 42
03 43
04 44
05 45
06 46
07 47
08 48
09 49
0A 4A
0B 0C 0D 4B 4C 4D
0E 4E
0F 4F
10 50
For Shift Right
27 67
00 40
01 41
02 42
03 43
04 44
05 45
06 46
07 47
08 48
09 49
0A 4A
0B 0C 0D 0E 4B 4C 4D 4E
216Figure 6 2-Line by 16-Character Display Example
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ST7066
Character Generator ROM (CGROM) The character generator ROM generates 5 x 8 dot or 5 x 11 dot character patterns from 8-bit character codes. It can generate 208 5 x 8 dot character patterns and 32 5 x 11 dot character patterns. User-defined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written, and for 5 x 11 dots, four character patterns can be written. Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM. See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area. LCD Driver Circuit LCD Driver circuit has 16 common and 40 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to 40 bit segment latch serially, and then it is stored to 40 bit shift latch. When each common is selected by 16 bit common register, segment data also output through segment driver from 40 bit segment latch. In case of 1-line display mode, COM1 ~ COM8 have 1/8 duty or COM1 ~ COM11 have 1/11duty , and in 2-line mode, COM1 ~ COM16 have 1/16 duty ratio. Cursor/Blink Control Circuit It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter.
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Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: 0A)
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Table 4(Cont.) (ROM Code: 0B)
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Character Code (DDRAM Data) b7 b6 b5 b4 b3 b3 b1 00 00 00 00 000000 00 00 00 00 00 00 00 000000 00 00 00 CGRAM Address b0 b5 b4 b3 b2 b1 0 00 0 00 0 01 0 01 000 0 10 0 10 0 11 0 11 1 00 1 00 1 01 1 01 000 1 10 1 10 1 11 1 11 Character Patterns (CGRAM Data) b0 b7 b6 b5 b4 b3 b2 b1 0 1111 1 0010 0 0010 1 0010 --0 0010 1 0010 0 0010 1 0000 0 1111 1 1000 0 1000 1 1111 --0 1010 1 1001 0 1000 1 0000
b0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns (CGRAM Data) Notes:
1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. "-": Indicates no effect.
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Instructions
There are four categories of instructions that: !" Designate ST7066 functions, such as display format, data length, etc. !" Set internal RAM addresses !" Perform data transfer with internal RAM !" Others
Instruction Table:
Instruction Code Instruction RS RW Clear Display DB DB DB DB DB DB DB DB 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 Write "20H" to DDRAM. and set DDRAM address to "00H" from AC Set DDRAM address to "00H" from AC Return Home 0 0 0 0 0 0 0 0 1 x and return cursor to its original position if shifted. The contents of DDRAM are not changed. Sets cursor move direction and Entry Mode Set 0 0 0 0 0 0 0 1 I/D S specifies display shift. These operations are performed during data write and read. Display ON/OFF Cursor or Display Shift Function Set Set CGRAM address Set DDRAM address Read Busy flag and address Write data to RAM Read data from RAM 0 1 BF 0 0 1 0 0 0 1 0 0 0 0 0 1 S/C R/L x x D=1: entire display on 0 0 0 0 0 0 1 D C B C=1: cursor on B=1: cursor position on Set cursor moving and display shift control bit, and the direction, without changing DDRAM data. DL: interface data is 8/4 bits 0 0 0 0 1 DL N F x x NL: number of line is 2/1 F: font size is 5x11/5x8 AC AC AC AC AC AC 5 4 3 2 1 0 Set CGRAM address in address counter 37 us 37 us 37 us 37 us 37 us 1.52 ms Description Description Time (270KHZ) 1.52 ms
0
0
AC AC AC AC AC AC AC Set DDRAM address in address counter 6 5 4 3 2 1 0 Whether during internal operation or not AC AC AC AC AC AC AC can be known by reading BF. The 6 5 4 3 2 1 0 contents of address counter can also be read.
37 us
0 us
1
0
D7 D6 D5 D4 D3 D2 D1 D0
Write data into internal RAM (DDRAM/CGRAM) Read data from internal RAM (DDRAM/CGRAM)
43 us
1
1
D7 D6 D5 D4 D3 D2 D1 D0
43 us
Note: Be sure the ST7066 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7066. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction execution time.
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INSTRUCTION DESCRIPTION
!" Clear Display
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). !" Return Home
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
0
1
x
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. !" Entry Mode Set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
1
I/D
S
Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when read from or write to CGRAM. S: Shift of entire display When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift left, I/D = "0" : shift right).
S H H
I/D H L
DESCRIPTION Shift the display to the left Shift the display to the right
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!" Display ON/OFF
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B : Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. !" Cursor or Display Shift
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
1
S/C R/L
x
x
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. S/C L L H H !" Function Set
Code
R/L L H L H Shift cursor to the left
Description
AC Value AC=AC-1 AC=AC+1 AC=AC
Shift cursor to the right Shift display to the left. Cursor follows the display shift
Shift display to the right. Cursor follows the display shift AC=AC
RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
DL
N
F
x
x
Control display/cursor/blink ON/OFF 1 bit register.
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DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. N : Display line number control bit When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. F : Display font type control bit When F = "Low", it means 5 x 8 dots format display mode When F = "High", 5 x11 dots format display mode. N L L H F L H x No. of Display Lines 1 1 2 Character Font 5x8 5x11 5x8 Duty Factor 1/8 1/11 1/16
!" Set CGRAM Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. !" Set DDRAM Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H".
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!" Read Busy Flag and Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
1
BF
AC6 AC5 AC4 AC3 AC2 AC1 AC0
When BF = "High", indicates that the internal operation is being processed.So during this time the next instruction cannot be accepted. The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. !" Write Data to CGRAM or DDRAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
1
0
D7 D6 D5 D4 D3 D2 D1 D0
Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. !" Read Data from CGRAM or DDRAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
1
1
D7 D6 D5 D4 D3 D2 D1 D0
Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction.
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Reset Function
Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the ST7066 when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 10 ms after VCC rises to 4.5 V. 1. Display clear 2. Function set: DL = 1; 8-bit interface data N = 0; 1-line display F = 0; 5 8 dot character font 3. Display on/off control: D = 0; Display off C = 0; Cursor off B = 0; Blinking off 4. Entry mode set: I/D = 1; Increment by 1 S = 0; No shift Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the ST7066. For such a case, initialization must be performed by the MPU as explain by the following figure.
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8-bit Interface:
Power On
Wait time > 15ms After Vcc > 4.5V
RS RW D7 D6 D5 D4 D3 D2 D1 D0 000011xxxx
BF cannot be checked before the Instruction Function set
Wait time > 4.1ms
000011xxxx
BF cannot be checked before the Instruction Function set
Wait time > 100us
000011xxxx
BF cannot be checked before the Instruction Function set
000011NFxx 0000001000 0000000001 0 0 0 0 0 0 0 1 I/D S
BF can be checked after the following Instructions Function Set Display Off Display Clear Entry mode set
Initialization End
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4-bit Interface:
Power On
Wait time > 15ms After Vcc > 4.5V
RS RW D7 D6 D5 D4 0 0 0 0 1 1
BF cannot be checked before the Instruction Function set
Wait time > 4.1ms
0
0
0
0
1
1
BF cannot be checked before the Instruction Function set
Wait time > 100us
0
0
0
0
1
1
BF cannot be checked before the Instruction Function set BF can be checked after the following Instructions Function Set
0
0
0
0
1
0 0 F 0 0 0 1
00001 0000N 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Display Off
Display Clear Entry mode set
000000 0 0 0 1 I/D S
Initialization End
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ST7066
Interfacing to the MPU
The ST7066 can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit MPU. !" For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the ST7066 and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. !" For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
Supply Voltage for LCD Drive
There are different voltages that supply to ST7066's pin (V1 - V5) to obtain LCD drive waveform. The relations of the bias, duty factor and supply voltages are shown as below: Duty Factor 1/8, 1/11 Bias Supply Voltage V1 V2 V3 V4 V5 1/4 Vcc - 1/4VLCD Vcc - 1/2VLCD Vcc - 1/2VLCD Vcc - 3/4VLCD Vcc - VLCD 1/5 Vcc - 1/5VLCD Vcc - 2/5VLCD Vcc - 3/5VLCD Vcc - 4/5VLCD Vcc- VLCD 1/16
1/4 bias (1/8, 1/11 duty cycle)
1/5 bias (1/16 duty cycle)
V5
V4
V3
V2
V1
Vcc
Vcc
V1
V2
V3
V4
V5
-5V
VR
R
R
R
R
+5V
R
R
R
R
R
VR
-5V
VLCD
VLCD
V1.2
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ST7066
Timing Characteristics
!" Writing data from MPU to ST7066
RS
VIH1 VIL1 TAH
R/W
TAS
TPW
TAH
E
TR TDSW Valid data TC TH
DB0-DB7
!" Reading data from ST7066 to MPU
RS
VIH1 VIL1 TAS TAH TAH
R/W
TR TPW
E
TDDR TH Valid data TC
DB0-DB7
V1.2
22
2000/6/13
ST7066
Absolute Maximum Ratings
Characteristics Power Supply Voltage LCD Driver Voltage Input Voltage Operating Temperature Storage Temperature
o
Symbol VCC VLCD VIN TA TSTO
Value -0.3V to +7.0V -0.3V to +13.0V -0.3V to VCC+0.3V -20 C to +70 C -55 C to +125 C
o o o o
DC Characteristics (TA = 25 C, VCC = 2.7V - 5.5V)
Symbol VCC VLCD ICC VIH1
Characteristics Operating Voltage LCD Voltage
Test Condition VCC-V5
Min. 2.7 3.0 2.2
Typ. 0.3 -
Max. 5.5 11 0.6 VCC
Unit V V mA V
Power Supply Current fOSC = 270KHz, VCC=5V Input High Voltage (Except OSC1) -
VIL1
Input Low Voltage (Except OSC1)
-
-0.3
-
0.6
V
VIH2
Input High Voltage (OSC1)
-
VCC-1
-
VCC
V
VIL2
Input Low Voltage (OSC2)
-
-
-
1.0
V
VOH1
Output High Voltage (DB0 - DB7)
IOH = -0.1mA
2.4
-
VCC
V
VOL1
Output Low Voltage (DB0 - DB7)
IOL = 0.1mA
-
-
0.4
V
VOH2
Output High Voltage (Except DB0 - DB7)
IOH = -0.04mA
0.9VCC
-
VCC
V
VOL2
Output Low Voltage (Except DB0 - DB7)
IOL = 0.04mA
-
-
0.1VCC
V
RCOM RSEG ILEAK
Common Resistance Segment Resistance Input Leakage Current
VLCD = 4V, Id = 0.05mA VLCD = 4V, Id = 0.05mA VIN = 0V to VCC
-1
2 2 -
20 30 1
K K A A
IPUP
Pull Up MOS Current
VCC = 5V
10
50
120
V1.2
23
2000/6/13
ST7066
AC Characteristics (TA = 25 C, VCC = 5V)
o
Symbol
Characteristics
Test Condition Internal Clock Operation
Min.
Typ.
Max.
Unit
fOSC
OSC Frequency
R = 91K External Clock Operation
190
270
350
KHz
fEX
External Frequency Duty Cycle -
125 45 -
250 50 -
350 55 0.2
KHz % s
TR,TF
Rise/Fall Time
Write Mode (Writing data from MPU to ST7066) TC TPW TR,TF TAS TAH TDSW TH Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW,E Address Hold Time Pins: RS,RW,E Data Setup Time Data Hold Time Pins: DB0 - DB7 Pins: DB0 - DB7 400 150 30 10 40 10 25 ns ns ns ns ns ns ns
Read Mode (Reading Data from ST7066 to MPU) TC TPW TR,TF TAS TAH TDDR TH Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW,E Address Hold Time Pins: RS,RW,E Data Setup Time Data Hold Time Pins: DB0 - DB7 Pins: DB0 - DB7 400 150 30 10 10 25 100 ns ns ns ns ns ns ns
Interface Mode with LCD Driver(ST7065) TCWH TCWL TCST TSU TDH TDM Clock Pulse with High Pins: CL1, CL2 Clock Pulse with Low Pins: CL1, CL2 Clock Setup Time Data Setup Time Data Hold Time M Delay Time Pins: CL1, CL2 Pin: D Pin: D Pin: M 800 800 500 300 300 -1000 1000 ns ns ns ns ns ns
V1.2
24
2000/6/13
ST7066
The relations between Oscillation Frequency and LCD Frame Frequency
Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us 1. 1/8 Duty
400 clocks
1
2
3
4
------
8
1
2
COM1
Vcc V1
V2(V3) V4 V5
1 frame
1 frame = 3.7(us) x 400 x 8 = 11850(us) = 11.9(ms)
2. 1/11 Duty
400 clocks
1
2
3
4
------
11
1
2
COM1
Vcc V1
V2(V3) V4 V5
1 frame
1 frame = 3.7(us) x 400 x 11 = 16300(us) = 16.3(ms)
3. 1/16 Duty
200 clocks
1
2
3
4
------
16
1
2
COM1
Vcc V1 V2 V3 V4 V5
1 frame
1 frame = 3.7(us) x 200 x 16 = 11850(us) = 11.9(ms)
V1.2
25
2000/6/13
ST7066
I/O PAD Configuration
Input PAD: E (No Pull-up)
Input PAD: RS, RW(with Pull-up)
Output PAD: CL1, CL2, M, D
Enable
DATA
I/O PAD: DB0 - DB7
V1.2
26
2000/6/13
ST7066
LCD and ST7066 Connection
1. 5x8 dots, 8 characters x 1 line (1/4 bias, 1/8 duty)
COM1 . . . . . COM8
ST7066
SEG1 . . . SEG40
LCD Panel: 8 Characters x 1 line
2. 5x11 dots, 8 characters x 1 line (1/4 bias, 1/11 duty)
ST7066
COM1 . . . . . . . . COM11
SEG1 . . . . . . . SEG40
LCD Panel: 8 Characters x 1 line
V1.2
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ST7066
3. 5x8 dots, 8 characters x 2 line (1/5 bias, 1/16 duty)
COM1 . . . . . COM8
ST7066
COM9 . . . . . COM16
SEG1 . . . . . . . SEG40
LCD Panel: 8 Characters x 2 line
4. 5x8 dots, 16 characters x 1 line (1/5 bias, 1/16 duty)
COM1 . . . . . COM8
ST7066
SEG1 . . . . SEG40 LCD Panel: 16 Characters x 1 line COM9 . . . . . COM16
V1.2
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Dot Matrix LCD Panel
COM1-16 D DL1 VDD FCS SHL1 SHL2 GND VEE V1 V2 V3
SEG1-40
Y1-Y40 DR2 DL2 DR1 CL1 CL2 M DL1 VDD FCS SHL1 SHL2 GND VEE
Y1-Y40
ST7065
ST7065
DR2 DL2 DR1 CL1 CL2 M
V4
V5
V6
V1
V2
V3
V4
V5
V6
ST7066 Application circuit
DB0-DB7
Reg.
To MPU Vcc(+5V )
Reg.
Reg.
Reg.
Reg.
Reg.
-V or GND
ST7066
Note: R= 2.2K ~ 10K, VR= 10K~30K
VCC GND CL2 CL1 M V1 V2 V3 V4 V5
V1.2
29
ST7066
2000/6/13

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